Difference between revisions of "CIA Memory Map"

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Line 7: Line 7:
 
! colspan="8" | Function
 
! colspan="8" | Function
 
|-
 
|-
! rowspan="18" | Odd CIA (CIA-A)
+
! rowspan="17" | Odd CIA (CIA-A)
| rowspan="2" | BFD000
+
| rowspan="2" | BFE001
 
| rowspan="2" | pra
 
| rowspan="2" | pra
 
! Bit 7
 
! Bit 7
Line 19: Line 19:
 
! Bit 0
 
! Bit 0
 
|-
 
|-
| _DTR
+
| _FIR1
(Serial port)
+
(Joystick port 1)
  
Data Terminal Ready
+
Port 1 fire button
| _RTS
+
| _FIR0
(Serial port)
+
(Joystick port 0)
  
Request To Send
+
Port 0 fire button
| _CD
+
| _RDY
(Serial port)
 
 
 
Carrier Detect
 
| _CTS
 
(Serial port)
 
 
 
Clear To Send
 
| _DSR
 
(Serial port)
 
 
 
Data Set Ready
 
| SEL
 
(Parallel port)
 
 
 
Select
 
| POUT
 
(Parallel port)
 
 
 
Paper Out
 
| BUSY
 
(Parallel port)
 
 
 
Busy
 
|-
 
| rowspan="2" | BFD100
 
| rowspan="2" | prb
 
! Bit 7
 
! Bit 6
 
! Bit 5
 
! Bit 4
 
! Bit 3
 
! Bit 2
 
! Bit 1
 
! Bit 0
 
|-
 
| _MTR
 
 
(Floppy drive)
 
(Floppy drive)
  
Motor on
+
Drive ready
| _SEL3
+
| _TK0
 
(Floppy drive)
 
(Floppy drive)
  
Select DF3:
+
Track 0 indicator
| _SEL2
+
| _WPRO
 
(Floppy drive)
 
(Floppy drive)
  
Select DF2:
+
Write protected
| _SEL1
+
| _CHNG
 
(Floppy drive)
 
(Floppy drive)
  
Select DF1:
+
Disk change signal
| _SEL0
+
| _LED
(Floppy drive)
+
(Audio filter)
  
Select DF0:
+
Audio filter enabled/disabled
| _SIDE
+
| OVL
(Floppy drive)
+
(Address decoding)
  
Side select
+
Sets ROM overlay on boot to map Kickstart to address 0
| DIR
+
|-
(Floppy drive)
+
| BFE101
 
+
| prb
Head direction
+
| colspan="8" | Parallel port data
| _STEP
 
(Floppy drive)
 
 
 
Step heads
 
 
|-
 
|-
| BFD200
+
| BFE201
 
| ddra
 
| ddra
 
| colspan="8" | Direction for Port A (BFD000), bit set = output
 
| colspan="8" | Direction for Port A (BFD000), bit set = output
 
|-
 
|-
| BFD300
+
| BFE301
 
| ddrb
 
| ddrb
 
| colspan="8" | Direction for Port B (BFD100), bit set = output
 
| colspan="8" | Direction for Port B (BFD100), bit set = output
 
|-
 
|-
| BFD400
+
| BFE401
 
| talo
 
| talo
 
| colspan="8" | Timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
 
| colspan="8" | Timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
 
|-
 
|-
| BFD500
+
| BFE501
 
| tahi
 
| tahi
 
| colspan="8" | Timer A high byte
 
| colspan="8" | Timer A high byte
 
|-
 
|-
| BFD600
+
| BFE601
 
| tblo
 
| tblo
 
| colspan="8" | Timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
 
| colspan="8" | Timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
 
|-
 
|-
| BFD700
+
| BFE701
 
| tbhi
 
| tbhi
 
| colspan="8" | Timer B high byte
 
| colspan="8" | Timer B high byte
 
|-
 
|-
| BFD800
+
| BFE801
 
| todlo
 
| todlo
| colspan="8" | Horizontal sync event counter bits 7-0
+
| colspan="8" | Vertical sync event counter bits 7-0 (50/60Hz)
 
|-
 
|-
| BFD900
+
| BFE901
 
| todmid
 
| todmid
| colspan="8" | Horizontal sync event counter bits 15-8
+
| colspan="8" | Vertical sync event counter bits 15-8
 
|-
 
|-
| BFDA00
+
| BFEA01
 
| todhi
 
| todhi
| colspan="8" | Horizontal sync event counter bits 23-16
+
| colspan="8" | Vertical sync event counter bits 23-16
 
|-
 
|-
| BFDB00
+
| BFEB01
 
|  
 
|  
 
| colspan="8" | Not used
 
| colspan="8" | Not used
 
|-
 
|-
| BFDC00
+
| BFEC01
 
| sdr
 
| sdr
| colspan="8" | Serial data register (not used)
+
| colspan="8" | Serial data register (used for keyboard)
 
|-
 
|-
| BFDD00
+
| BFED01
 
| icr
 
| icr
 
| colspan="8" | Interrupt control register
 
| colspan="8" | Interrupt control register
 
|-
 
|-
| BFDE00
+
| BFEE01
 
| cra
 
| cra
 
| colspan="8" | Control register A
 
| colspan="8" | Control register A
 
|-
 
|-
| BFDF00
+
| BFEF01
 
| crb
 
| crb
 
| colspan="8" | Control register B
 
| colspan="8" | Control register B

Revision as of 15:52, 22 September 2016

All accesses must be in single bytes.

CIA Address Register Function
Odd CIA (CIA-A) BFE001 pra Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
_FIR1

(Joystick port 1)

Port 1 fire button

_FIR0

(Joystick port 0)

Port 0 fire button

_RDY

(Floppy drive)

Drive ready

_TK0

(Floppy drive)

Track 0 indicator

_WPRO

(Floppy drive)

Write protected

_CHNG

(Floppy drive)

Disk change signal

_LED

(Audio filter)

Audio filter enabled/disabled

OVL

(Address decoding)

Sets ROM overlay on boot to map Kickstart to address 0

BFE101 prb Parallel port data
BFE201 ddra Direction for Port A (BFD000), bit set = output
BFE301 ddrb Direction for Port B (BFD100), bit set = output
BFE401 talo Timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFE501 tahi Timer A high byte
BFE601 tblo Timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFE701 tbhi Timer B high byte
BFE801 todlo Vertical sync event counter bits 7-0 (50/60Hz)
BFE901 todmid Vertical sync event counter bits 15-8
BFEA01 todhi Vertical sync event counter bits 23-16
BFEB01 Not used
BFEC01 sdr Serial data register (used for keyboard)
BFED01 icr Interrupt control register
BFEE01 cra Control register A
BFEF01 crb Control register B
Even CIA (CIA-B) BFD000 pra Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
_DTR

(Serial port)

Data Terminal Ready

_RTS

(Serial port)

Request To Send

_CD

(Serial port)

Carrier Detect

_CTS

(Serial port)

Clear To Send

_DSR

(Serial port)

Data Set Ready

SEL

(Parallel port)

Select

POUT

(Parallel port)

Paper Out

BUSY

(Parallel port)

Busy

BFD100 prb Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
_MTR

(Floppy drive)

Motor on

_SEL3

(Floppy drive)

Select DF3:

_SEL2

(Floppy drive)

Select DF2:

_SEL1

(Floppy drive)

Select DF1:

_SEL0

(Floppy drive)

Select DF0:

_SIDE

(Floppy drive)

Side select

DIR

(Floppy drive)

Head direction

_STEP

(Floppy drive)

Step heads

BFD200 ddra Direction for Port A (BFD000), bit set = output
BFD300 ddrb Direction for Port B (BFD100), bit set = output
BFD400 talo Timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFD500 tahi Timer A high byte
BFD600 tblo Timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFD700 tbhi Timer B high byte
BFD800 todlo Horizontal sync event counter bits 7-0
BFD900 todmid Horizontal sync event counter bits 15-8
BFDA00 todhi Horizontal sync event counter bits 23-16
BFDB00 Not used
BFDC00 sdr Serial data register (not used)
BFDD00 icr Interrupt control register
BFDE00 cra Control register A
BFDF00 crb Control register B