Difference between revisions of "CIA Memory Map"

From Amiga Coding
Jump to: navigation, search
m (Corrected port reference on odd CIA direction register)
 
Line 58: Line 58:
 
| BFE201
 
| BFE201
 
| ddra
 
| ddra
| colspan="8" | Direction for Port A (BFD000), bit set = output
+
| colspan="8" | Direction for Port A (BFD001), bit set = output
 
|-
 
|-
 
| BFE301
 
| BFE301
 
| ddrb
 
| ddrb
| colspan="8" | Direction for Port B (BFD100), bit set = output
+
| colspan="8" | Direction for Port B (BFD101), bit set = output
 
|-
 
|-
 
| BFE401
 
| BFE401

Latest revision as of 22:02, 27 June 2018

All accesses must be in single bytes.

CIA Address Register Function
Odd CIA (CIA-A) BFE001 pra Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
_FIR1

(Joystick port 1)

Port 1 fire button

_FIR0

(Joystick port 0)

Port 0 fire button

_RDY

(Floppy drive)

Drive ready

_TK0

(Floppy drive)

Track 0 indicator

_WPRO

(Floppy drive)

Write protected

_CHNG

(Floppy drive)

Disk change signal

_LED

(Audio filter)

Audio filter enabled/disabled

OVL

(Address decoding)

Sets ROM overlay on boot to map Kickstart to address 0

BFE101 prb Parallel port data
BFE201 ddra Direction for Port A (BFD001), bit set = output
BFE301 ddrb Direction for Port B (BFD101), bit set = output
BFE401 talo Timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFE501 tahi Timer A high byte
BFE601 tblo Timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFE701 tbhi Timer B high byte
BFE801 todlo Vertical sync event counter bits 7-0 (50/60Hz)
BFE901 todmid Vertical sync event counter bits 15-8
BFEA01 todhi Vertical sync event counter bits 23-16
BFEB01 Not used
BFEC01 sdr Serial data register (used for keyboard)
BFED01 icr Interrupt control register
BFEE01 cra Control register A
BFEF01 crb Control register B
Even CIA (CIA-B) BFD000 pra Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
_DTR

(Serial port)

Data Terminal Ready

_RTS

(Serial port)

Request To Send

_CD

(Serial port)

Carrier Detect

_CTS

(Serial port)

Clear To Send

_DSR

(Serial port)

Data Set Ready

SEL

(Parallel port)

Select

POUT

(Parallel port)

Paper Out

BUSY

(Parallel port)

Busy

BFD100 prb Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
_MTR

(Floppy drive)

Motor on

_SEL3

(Floppy drive)

Select DF3:

_SEL2

(Floppy drive)

Select DF2:

_SEL1

(Floppy drive)

Select DF1:

_SEL0

(Floppy drive)

Select DF0:

_SIDE

(Floppy drive)

Side select

DIR

(Floppy drive)

Head direction

_STEP

(Floppy drive)

Step heads

BFD200 ddra Direction for Port A (BFD000), bit set = output
BFD300 ddrb Direction for Port B (BFD100), bit set = output
BFD400 talo Timer A low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFD500 tahi Timer A high byte
BFD600 tblo Timer B low byte (.715909 Mhz NTSC; .709379 Mhz PAL)
BFD700 tbhi Timer B high byte
BFD800 todlo Horizontal sync event counter bits 7-0
BFD900 todmid Horizontal sync event counter bits 15-8
BFDA00 todhi Horizontal sync event counter bits 23-16
BFDB00 Not used
BFDC00 sdr Serial data register (not used)
BFDD00 icr Interrupt control register
BFDE00 cra Control register A
BFDF00 crb Control register B